module Traffic(clk,rst_p,row,col_green,col_red,cat_8,seg_8);
input clk;    
input rst_p;  

output [7:0] row,col_green,col_red;  
output [7:0] cat_8;                  
output [7:0] seg_8;                  

reg [7:0] row,col_green,col_red;
reg [7:0] cat_8; 
reg [7:0] seg_8;
reg [8:0] div_cnt;     
reg clk_1Hz;           
reg [5:0] state_cnt;   
reg [2:0] state;       
reg [2:0] row_cnt;     
reg [1:0] cat_cnt;     
reg [4:0] time1,time1_standard; 
reg [4:0] time2,time2_standard; 
reg [4:0] seg_data;    


wire [4:0] time1_shi,time1_ge,time2_shi,time2_ge; 
assign time1_shi=time1/4'd10;
assign time1_ge=time1%4'd10;
assign time2_shi=time2/4'd10;
assign time2_ge=time2%4'd10;


always@(posedge clk or posedge rst_p)
begin
  if(rst_p)
    begin
      div_cnt<=9'd0;
      clk_1Hz<=1'b1; 
    end
  else
    begin
      if(div_cnt==9'd499)
	    begin
	      div_cnt<=9'd0;
	      clk_1Hz<=!clk_1Hz;
	    end
	  else
	    div_cnt<=div_cnt+9'd1;
    end  	      
end


always@(posedge clk_1Hz or posedge rst_p)
begin   
  if(rst_p)
    state_cnt<=6'd0;
  else
    begin
      if(state==3'd0)
        begin
          if(state_cnt==6'd2)
	        state_cnt<=6'd0;
	      else
		    state_cnt<=state_cnt+6'd1;
        end        
      else
        begin
          if(state_cnt==6'd39)
	        state_cnt<=6'd0;
	      else
		    state_cnt<=state_cnt+6'd1;
        end  
    end		
end



always@(posedge clk_1Hz or posedge rst_p)
begin
  if(rst_p)
    state<=3'd0;
  else
    begin
      case(state)
        3'd0 : begin 
                 if(state_cnt==6'd2)
                   state<=3'd1;       
                 else
                   state<=state;
               end
               
        3'd1 : begin 
                 if(state_cnt==6'd14)
                   state<=3'd2;       
                 else
                   state<=state;
               end
               
        3'd2 : begin 
                 if(state_cnt==6'd19)
                   state<=3'd3;       
                 else
                   state<=state;
               end
               
        3'd3 : begin 
                 if(state_cnt==6'd34)
                   state<=3'd4;       
                 else
                   state<=state;
               end
               
        3'd4 : begin 
                 if(state_cnt==6'd39)
                   state<=3'd1;       
                 else
                   state<=state;
               end
         
        default : state<=state;    
      endcase                                
    end
end


always@(posedge clk or posedge rst_p)
begin   
  if(rst_p)
    row_cnt<=3'd0;
  else
    begin
      if(row_cnt==3'd7)
	    row_cnt<=3'd0;
	  else
		row_cnt<=row_cnt+3'd1;         
    end		
end

always@(*)
begin
  if(rst_p)
    begin
      row=8'b0000_0000;
      col_green=8'b0000_0000;
      col_red=8'b0000_0000;
    end
  else
    begin
      case(row_cnt)
        3'd0 : begin
                 row=8'b0111_1111;
                 case(state)
                   3'd0 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0110; end
                   3'd1 : begin col_green=8'b0000_0110 ; col_red=8'b0000_0000; end
                   3'd2 : begin col_green=8'b0000_0110 ; col_red=8'b0000_0110; end
                   3'd3 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0110; end
                   3'd4 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0110; end
                   default : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end 
                 endcase  
               end
               
        3'd1 : begin
                 row=8'b1011_1111;
                 case(state)
                   3'd0 : begin col_green=8'b0000_0000 ; col_red=8'b1100_0110; end
                   3'd1 : begin col_green=8'b0000_0110 ; col_red=8'b1100_0000; end
                   3'd2 : begin col_green=8'b0000_0110 ; col_red=8'b1100_0110; end
                   3'd3 : begin col_green=8'b1100_0000 ; col_red=8'b0000_0110; end
                   3'd4 : begin col_green=8'b1100_0000 ; col_red=8'b1100_0110; end
                   default : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end 
                 endcase
               end 
                 
        3'd2 : begin
                 row=8'b1101_1111;
                 case(state)
                   3'd0 : begin col_green=8'b0000_0000 ; col_red=8'b1100_0000; end
                   3'd1 : begin col_green=8'b0000_0000 ; col_red=8'b1100_0000; end
                   3'd2 : begin col_green=8'b0000_0000 ; col_red=8'b1100_0000; end
                   3'd3 : begin col_green=8'b1100_0000 ; col_red=8'b0000_0000; end                  
                   3'd4 : begin col_green=8'b1100_0000 ; col_red=8'b1100_0000; end
                   default : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end 
                 endcase
               end       
               
        3'd3 : begin
                 row=8'b1110_1111;
                 case(state)
                   3'd0 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                   3'd1 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                   3'd2 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                   3'd3 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end                  
                   3'd4 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                   default : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                 endcase
               end       
               
        3'd4 : begin
                 row=8'b1111_0111;
                 case(state)
                   3'd0 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                   3'd1 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                   3'd2 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                   3'd3 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end                  
                   3'd4 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                   default : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                 endcase
               end       
               
        3'd5 : begin
                 row=8'b1111_1011;
                 case(state)
                   3'd0 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0011; end
                   3'd1 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0011; end
                   3'd2 : begin col_green=8'b0000_0000 ; col_red=8'b0000_0011; end
                   3'd3 : begin col_green=8'b0000_0011 ; col_red=8'b0000_0000; end                  
                   3'd4 : begin col_green=8'b0000_0011 ; col_red=8'b0000_0011; end
                   default : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                 endcase
               end
               
        3'd6 : begin
                 row=8'b1111_1101;
                 case(state)
                   3'd0 : begin col_green=8'b0000_0000 ; col_red=8'b0110_0011; end
                   3'd1 : begin col_green=8'b0110_0000 ; col_red=8'b0000_0011; end
                   3'd2 : begin col_green=8'b0110_0000 ; col_red=8'b0110_0011; end
                   3'd3 : begin col_green=8'b0000_0011 ; col_red=8'b0110_0000; end                  
                   3'd4 : begin col_green=8'b0000_0011 ; col_red=8'b0110_0011; end
                   default : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                 endcase
               end       
               
        3'd7 : begin
                 row=8'b1111_1110;
                 case(state)
                   3'd0 : begin col_green=8'b0000_0000 ; col_red=8'b0110_0000; end
                   3'd1 : begin col_green=8'b0110_0000 ; col_red=8'b0000_0000; end
                   3'd2 : begin col_green=8'b0110_0000 ; col_red=8'b0110_0000; end
                   3'd3 : begin col_green=8'b0000_0000 ; col_red=8'b0110_0000; end                  
                   3'd4 : begin col_green=8'b0000_0000 ; col_red=8'b0110_0000; end
                   default : begin col_green=8'b0000_0000 ; col_red=8'b0000_0000; end
                 endcase
               end       
      endcase                    
    end
end

always@(posedge clk_1Hz or posedge rst_p) 
begin
  if(rst_p)
    begin
      time1_standard<=5'd2;
      time2_standard<=5'd2;
    end
  else
    begin
      if(state==3'd0)
        begin
          if(state_cnt==6'd1)
            begin
              time1_standard<=5'd14;
              time2_standard<=5'd19;
            end
        end
      else
        begin
          case(state_cnt)
            6'd38 : begin time1_standard<=5'd14;time2_standard<=5'd19; end
            6'd13 : begin time1_standard<=5'd4;time2_standard<=5'd19;  end
            6'd18 : begin time1_standard<=5'd19;time2_standard<=5'd14; end
            6'd33 : begin time1_standard<=5'd19;time2_standard<=5'd4;  end
            default : begin time1_standard<=time1_standard;time2_standard<=time2_standard;end
          endcase      
        end          
    end	
end

always@(posedge clk_1Hz or posedge rst_p)  
begin
  if(rst_p)
    time1<=time1_standard;
  else
    begin
      if(time1==5'd0)
        time1<=time1_standard;
      else
        time1<=time1-5'd1;    
    end
end

always@(posedge clk_1Hz or posedge rst_p)  
begin
  if(rst_p)
    time2<=time2_standard;
  else
    begin
      if(time2==5'd0)
        time2<=time2_standard;
      else
        time2<=time2-5'd1;    
    end
end

always@(posedge clk or posedge rst_p)
begin
  if(rst_p)
    cat_cnt<=2'd0;
  else
    begin
      if(cat_cnt==2'd3)
	    cat_cnt<=2'd0;
	  else
		cat_cnt<=cat_cnt+2'd1;         
    end	
end

always@(*)
begin
  if(rst_p)
    begin
      cat_8=8'b1111_1111;
      seg_data=4'd0;
    end
  else
    begin
      case(cat_cnt)
        2'd0 : begin
                 cat_8=8'b0111_1111;
                 seg_data=time1_shi;  
               end
               
        2'd1 : begin
                 cat_8=8'b1011_1111;
                 seg_data=time1_ge;   
               end
               
        2'd2 : begin
                 cat_8=8'b1111_1101;
                 seg_data=time2_shi;  
               end
               
        2'd3 : begin
                 cat_8=8'b1111_1110;
                 seg_data=time2_ge;   
               end
      endcase  
    end  
end

always@(*)
begin
  if(rst_p)
    seg_8=8'b0000_0000;
  else
    begin
      case(seg_data)
        5'd0 : seg_8=8'b0011_1111;
        5'd1 : seg_8=8'b0000_0110;
        5'd2 : seg_8=8'b0101_1011;
        5'd3 : seg_8=8'b0100_1111;
        5'd4 : seg_8=8'b0110_0110;
        5'd5 : seg_8=8'b0110_1101;
        5'd6 : seg_8=8'b0111_1101;
        5'd7 : seg_8=8'b0000_0111;
        5'd8 : seg_8=8'b0111_1111;
        5'd9 : seg_8=8'b0110_1111;
        default : seg_8=8'b0000_0000;
      endcase
    end
end

endmodule
